Adaptive Dead-Time Control Design with Low Dead-Time Error in 20 MHz 90 V GaN Gate Driver

This paper presents an adaptive dead-time control circuit for a maximum work frequency 20 MHz, voltage level 90 V GaN gate driver. The is set to prevent straight-through of the upper and lower power transistors bridge arm structure ensure reliability motor For drivers on market today, fixed or configurable widely used in more-than-10 MHz application scenarios. However, switching loss caused by insufficient reverse turn-on excessive devices have hazardous influence efficiency drivers, which cannot avoid. driver with proposed has been implemented 0.18 um BCD process. dissipates 56.3 uA quiescent current simulation situation able provide 5 ns error